
V 0.3

Audience
	s/w engineers familiar with DSP concepts who are interested
		in building signal processing systems
	Research, education in signal processing concepts

Introduction 
	What is pspectra?
		Move digital interface to antenna
		Minimize the use of specialized h/w
		investigate adaptive systems
			actual situation, not worst case nor average
		Statistical real time
			use buffering to handle jitter
		Apply principles of software engineering to signal processing
		Use general purpose o/s - Linux
	Who will use it?
		signal processing application design
			wireless -  software radio
			ultrasound
		Advantages of pspectra
			rapid deployment
			integration
			flexibility
			reduced cost for specialized devices
			easy, in-field upgrade
			adaptation
		Disadvantages of pspectra
			power
			size
	Outline of system.
		SMP GPP
		special h/w
		goal directed scheduling/processing
		cache aware

Overall design
	Data pull, goal directed architecture
	Separation of processing, buffer management, control
	Library of composable modules
	Buffer management
		use of mmap to make buffers circular
	Scheduling
		2 phase architecture
			forecast
			process
	GUI design
	History for FIR calculations
	Out-of-band control processing
	Type derivation tree
		VrSigProc_base
			VrSigProc
				VrSink
				VrSource
				Decimating
					other processing modules
				History
					other processing modules
				Interpolating
					other processing modules
				other processing modules
		VrBuffer
		VrConnect
		VrMultiTask

Construction of an application
	Application outline
		declare modules
		'connect' modules
		'start' sink
		loop on 'process'
		on termination, call 'stop' if needed
	Define processing computation
	Define user interface
	Construct processing chain
	Test with file data
	Test with live data
	Performance tuning

Construction of a module
	Module outline
		initialize
		forecast
		work
	Type definition
		Derived from VrSigProc
			output VrBuffer
			input VrConnect
	Timestamps
	Buffer format, sizes, processing
	Multiple inputs/outputs
	Multithread compatibility
		sync()
		forecast, work should work together
	Source processing
	Sink processing
	Commonly used derived types
		History
		Decimating
		Interpolating
	Example
		VrAmp

Detailed design
	Scheduling
	Multithread - see Brett's thesis!
	Asynchronous packet processing

Algorithms
	FIR vs IIR
	Complex FIR filter
		downconversion combined with bandpass filter
	Table driven transmit waveform generation

Hardware interface
	Hardware design (simple)
		Wideband A/D and D/A
		Page-based DMA interface at PCI bus rate 900mbps,
			application rate 500mbps
		high sustained data rates
	Device driver design
	Device driver ioctl interface
 		a file descriptor must be only for reading OR writing, not both
		 GIOCSETBUFSIZE  unsigned int
			Set standard buffer size to some number of pages
		 GIOCSTART 
			Start up the DMA/interrupt driver
		 GIOCSTOP  
			Stop the DMA/interrupt driver
		 GIOCSETGETSTATUS struct guppi_status
			Tell the driver that the user is done with a range of pages
			Get the range of pages available for the user and
				the number of overruns since last call

			struct guppi_status {
  				unsigned int index;
					index of the first valid page
						(this page is valid if num > 0)
  				unsigned int num;
					number of valid pages starting at index
  				unsigned int lost; 
  					number of pages thrown away because the buffer
						was full since the last status check
  					if this is >0 then num should equal the
  						number of pages in the entire buffer
			};
	Guppi source
	Guppi sink

System definitions
	VrBuffer.h VrBuffer.cc
	VrConnect.h
	VrObj.h VrObj.cc
	VrSigProc.h VrSigProc_base.h

	VrSink.h
	VrSource.h

	VrCycleCount.h

	VrTypes.h
	VrComplex.h VrComplex.cc


	VrMultiTask.h VrMultiTask.cc

I/O Module definitions

	VrSkippingSink.h

	VrAudioSink.h
	VrAudioSource.h
	VrFileSink.h
	VrFileSource.h
	VrGuppiBuffer.h
	VrGuppiSink.h
	VrPcvfoSink.h
	VrGuppiSource.h
	VrAR5000Source.h
	VrSigSource.h

	VrNullSink.h
	VrPerfGraph.h VrPerfGraph.cc

	VrGnuPlotSink.h
	VrFFTSink.h

Processing Module definitions
	VrDecimatingSigProc.h
	VrHistoryProc.h
	VrInterpolatingSigProc.h

	VrAmplitudeDemod.h
	VrComplexFIRfilter.h
	VrRealFIRfilter.h
	VrMixer.h
	VrSum.h
	VrQuadratureDemod.h
	VrAmp.h

	VrAMMod.h
	VrAWGN.h
	VrComplexCascadefilter.h
	VrCobsZpeStuff.h VrCobsZpeUnStuff.h
	VrDownSample.h
	VrFMMod.h VrFHFSKMod.h VrFHFSKDemod.h
	VrFSKMod.h VrFSKDemod.h
	VrHoppingComplexFIRfilter.h
	VrIIRfilter.h
	VrSquelch.h

MMX Module definitions
	VrAdd_MMX.s VrAdd4_MMX.s
	VrMMX.h VrMMX.s
	VrFMMul.s

Softlink Module definitions
	VrSoftLinkSink.h
	VrSoftLinkSource.h
	VrIPpacket.h VrIPpacket.cc
	Softlink device driver

Sample applications
	AMPS receiver
	multiband
	TV
	PAM

History
	GSM receiver design
	Viewsystem

Future work
	Rockwell receiver/transmitter
	Application of OSI RM for wireless
		Partition of functions
		'Layering' the physical layer
	Asynchronous packets - tight integration w/ TCP/IP
	Cache oblivious

List of files???


exported functions
	getMarkedWP() returns the first timestamp after currently scheduled work
		(for synchronizing computation source/sink)
	overridable functions for recursive module definitions
		connect(3 parameter)
			override in containing module to call connect() in
				contained modules
		getOutputBuffer()
			override in containing module to call getOutputBuffer()
				in last contained module

Work to do
	change the scheduler so that if a module does not finish
		its requested calculation, the sink is rerun with the
		requested size cut in half.  Note that this can only
		be used on sync()'ed streams (threading won't work)

