patch-2.1.82 linux/arch/alpha/kernel/pyxis.c

• Lines: 49
• Date: Sun Jan 25 10:35:16 1998
• Orig file: v2.1.81/linux/arch/alpha/kernel/pyxis.c
• Orig date: Mon Jan 12 14:51:14 1998

diff -u --recursive --new-file v2.1.81/linux/arch/alpha/kernel/pyxis.c linux/arch/alpha/kernel/pyxis.c
@@ -16,6 +16,10 @@
 #include <asm/ptrace.h>
 #include <asm/mmu_context.h>
 
+/* NOTE: Herein are back-to-back mb insns.  They are magic.
+   A plausible explanation is that the i/o controler does not properly
+   handle the system transaction.  Another involves timing.  Ho hum.  */
+
 extern struct hwrpb_struct *hwrpb;
 extern asmlinkage void wrmces(unsigned long mces);
 extern int alpha_sys_type;
@@ -153,6 +157,7 @@
 	/* access configuration space: */
 	value = *(vuip)addr;
 	mb();
+	mb();  /* magic */
 	if (PYXIS_mcheck_taken) {
 		PYXIS_mcheck_taken = 0;
 		value = 0xffffffffU;
@@ -228,6 +233,7 @@
 	/* access configuration space: */
 	*(vuip)addr = value;
 	mb();
+	mb();  /* magic */
 	PYXIS_mcheck_expected = 0;
 	mb();
 
@@ -473,11 +479,13 @@
 	 * ignore the machine check.
 	 */
 	mb();
+	mb();  /* magic */
 	if (PYXIS_mcheck_expected/* && (mchk_sysdata->epic_dcsr && 0x0c00UL)*/) {
 		DBG(("PYXIS machine check expected\n"));
 		PYXIS_mcheck_expected = 0;
 		PYXIS_mcheck_taken = 1;
 		mb();
+		mb();  /* magic */
 		draina();
 		pyxis_pci_clr_err();
 		wrmces(0x7);
@@ -494,6 +502,7 @@
 		PYXIS_mcheck_expected = 0;
 		PYXIS_mcheck_taken = 1;
 		mb();
+		mb();  /* magic */
 		draina();
 		pyxis_pci_clr_err();
 		wrmces(0x7);