patch-2.2.18 linux/arch/arm/lib/checksum.S

• Lines: 188
• Date: Fri Sep 15 23:28:37 2000
• Orig file: v2.2.17/arch/arm/lib/checksum.S
• Orig date: Fri Apr 21 12:45:45 2000

diff -u --new-file --recursive --exclude-from /usr/src/exclude v2.2.17/arch/arm/lib/checksum.S linux/arch/arm/lib/checksum.S
@@ -74,8 +74,9 @@
 		stmfd	sp!, {r1 - r2, r4 - r8, fp, ip, lr, pc}
 		.endm
 
-#define LOAD_REGS(cond)					\
-		LOADREGS(##cond##ea,fp,{r1 - r2, r4 - r8, fp, sp, pc})
+		.macro	load_regs,flags
+		ldm\flags	fp, {r1, r2, r4-r8, fp, sp, pc}
+		.endm
 
 		.macro	load1b,	reg1
 9999:		ldrbt	\reg1, [r0], $1
@@ -130,12 +131,13 @@
 		stmfd	sp!, {r1 - r2, r4 - r9, fp, ip, lr, pc}
 		mov	r9, sp, lsr #13
 		mov	r9, r9, lsl #13
-		ldr	r9, [r9, #TSK_ADDR_LIMIT]
+		ldr	r9, [r9, #ADDR_LIMIT]
 		mov	r9, r9, lsr #24
 		.endm
 
-#define LOAD_REGS(cond)					\
-		LOADREGS(##cond##ea,fp,{r1 - r2, r4 - r9, fp, sp, pc})
+		.macro	load_regs,flags
+		ldm\flags	fp, {r1, r2, r4-r9, fp, sp, pc}^
+		.endm
 
 		.macro	load1b,	reg1
 		tst	r9, #0x01
@@ -245,7 +247,7 @@
 		adcs	r3, r3, r4
 4:		ands	r2, r2, #3
 		adceq	r0, r3, #0
-		LOAD_REGS(eq)
+		load_regs	eqea
 		load1l	r4
 		tst	r2, #2
 		beq	.exit
@@ -259,11 +261,11 @@
 		andne	r4, r4, #255
 		adcnes	r3, r3, r4
 		adcs	r0, r3, #0
-		LOAD_REGS(al)
+		load_regs	ea
 
 .too_small_user:
 		teq	r2, #0
-		LOAD_REGS(eq)
+		load_regs	eqea
 		cmp	r2, #2
 		blt	.too_small_user1
 		load2b	ip, r8
@@ -278,7 +280,7 @@
 		strb	ip, [r1], #1
 		adcs	r3, r3, ip
 .csum_exit:	adc	r0, r3, #0
-		LOAD_REGS(al)
+		load_regs	ea
 
 .src_not_aligned_user:
 		cmp	r2, #4
@@ -331,7 +333,7 @@
 		mov	r4, r5, lsr #8
 4:		ands	r2, r2, #3
 		adceq	r0, r3, #0
-		LOAD_REGS(eq)
+		load_regs	eqea
 		tst	r2, #2
 		beq	.exit
 		adcs	r3, r3, r4, lsl #16
@@ -384,13 +386,16 @@
 		mov	r4, r5, lsr #16
 4:		ands	r2, r2, #3
 		adceq	r0, r3, #0
-		LOAD_REGS(eq)
+		load_regs	eqea
 		tst	r2, #2
 		beq	.exit
 		adcs	r3, r3, r4, lsl #16
 		strb	r4, [r1], #1
 		mov	r4, r4, lsr #8
 		strb	r4, [r1], #1
+		tst	r2, #1
+		adceq	r0, r3, #0
+		load_regs	eqea
 		load1b	r4
 		b	.exit
 
@@ -437,7 +442,7 @@
 		mov	r4, r5, lsr #24
 4:		ands	r2, r2, #3
 		adceq	r0, r3, #0
-		LOAD_REGS(eq)
+		load_regs	eqea
 		tst	r2, #2
 		beq	.exit
 		adcs	r3, r3, r4, lsl #16
@@ -461,7 +466,7 @@
 6002:		teq	r2, r1
 		strneb	r3, [r1], #1
 		bne	6002b
-		LOAD_REGS(al)
+		load_regs	ea
 #if defined(CONFIG_CPU_32)
 		.previous
 #endif
@@ -520,13 +525,13 @@
 		LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})
 		ldr	r4, [r0], #4
 		tst	r2, #2
-		beq	Lexit
+		beq	Lexit_r4
 		adcs	r3, r3, r4, lsl #16
 		strb	r4, [r1], #1
 		mov	r4, r4, lsr #8
 		strb	r4, [r1], #1
 		mov	r4, r4, lsr #8
-		b	Lexit
+		b	Lexit_r4
 
 Ltoo_small:	teq	r2, #0
 		LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})
@@ -538,10 +543,12 @@
 		adds	r3, r3, ip
 		strb	ip, [r1], #1
 		strb	r8, [r1], #1
-Lexit:		tst	r2, #1
-Ltoo_small1:	ldrneb	ip, [r0], #1
-		strneb	ip, [r1], #1
-		adcnes	r3, r3, ip
+		tst	r2, #1
+Ltoo_small1:	ldrneb	r4, [r0], #1
+Lexit_r4:	tst	r2, #1
+		strneb	r4, [r1], #1
+		andne	r4, r4, #255
+		adcnes	r3, r3, r4
 		adcs	r0, r3, #0
 		LOADREGS(ea,fp,{r4 - r8, fp, sp, pc})
 
@@ -598,13 +605,13 @@
 		adceq	r0, r3, #0
 		LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})
 		tst	r2, #2
-		beq	Lexit
+		beq	Lexit_r4
 		adcs	r3, r3, r4, lsl #16
 		strb	r4, [r1], #1
 		mov	r4, r4, lsr #8
 		strb	r4, [r1], #1
 		mov	r4, r4, lsr #8
-		b	Lexit
+		b	Lexit_r4
 
 Lsrc2_aligned:	mov	r4, r4, lsr #16
 		adds	r3, r3, #0
@@ -650,13 +657,13 @@
 		adceq	r0, r3, #0
 		LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})
 		tst	r2, #2
-		beq	Lexit
+		beq	Lexit_r4
 		adcs	r3, r3, r4, lsl #16
 		strb	r4, [r1], #1
 		mov	r4, r4, lsr #8
 		strb	r4, [r1], #1
 		ldrb	r4, [r0], #1
-		b	Lexit
+		b	Lexit_r4
 
 Lsrc3_aligned:	mov	r4, r4, lsr #24
 		adds	r3, r3, #0
@@ -702,14 +709,14 @@
 		adceq	r0, r3, #0
 		LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})
 		tst	r2, #2
-		beq	Lexit
+		beq	Lexit_r4
 		adcs	r3, r3, r4, lsl #16
 		strb	r4, [r1], #1
 		ldr	r4, [r0], #4
 		strb	r4, [r1], #1
 		adcs	r3, r3, r4, lsl #24
 		mov	r4, r4, lsr #8
-		b	Lexit
+		b	Lexit_r4
 
 ENTRY(__csum_ipv6_magic)
 		stmfd	sp!, {lr}