patch-2.1.79 linux/arch/alpha/kernel/apecs.c

• Lines: 237
• Date: Mon Jan 12 14:51:14 1998
• Orig file: v2.1.78/linux/arch/alpha/kernel/apecs.c
• Orig date: Mon Oct 7 02:40:22 1996

diff -u --recursive --new-file v2.1.78/linux/arch/alpha/kernel/apecs.c linux/arch/alpha/kernel/apecs.c
@@ -21,12 +21,11 @@
 extern struct hwrpb_struct *hwrpb;
 extern asmlinkage void wrmces(unsigned long mces);
 extern int alpha_sys_type;
+
 /*
  * BIOS32-style PCI interface:
  */
 
-#ifdef CONFIG_ALPHA_APECS
-
 #ifdef DEBUG
 # define DBG(args)	printk args
 #else
@@ -88,7 +87,8 @@
 {
 	unsigned long addr;
 
-	DBG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, pci_addr=0x%p, type1=0x%p)\n",
+	DBG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
+	     " pci_addr=0x%p, type1=0x%p)\n",
 	     bus, device_fn, where, pci_addr, type1));
 
 	if (bus == 0) {
@@ -97,7 +97,8 @@
 		/* type 0 configuration cycle: */
 
 		if (device > 20) {
-			DBG(("mk_conf_addr: device (%d) > 20, returning -1\n", device));
+			DBG(("mk_conf_addr: device (%d) > 20, returning -1\n",
+			     device));
 			return -1;
 		}
 
@@ -142,15 +143,15 @@
 	DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
 
 	/* reset status register to avoid losing errors: */
-	stat0 = *((volatile unsigned int *)APECS_IOC_DCSR);
-	*((volatile unsigned int *)APECS_IOC_DCSR) = stat0;
+	stat0 = *(vuip)APECS_IOC_DCSR;
+	*(vuip)APECS_IOC_DCSR = stat0;
 	mb();
 	DBG(("conf_read: APECS DCSR was 0x%x\n", stat0));
 	/* if Type1 access, must set HAE #2 */
 	if (type1) {
-		haxr2 = *((unsigned int *)APECS_IOC_HAXR2);
+		haxr2 = *(vuip)APECS_IOC_HAXR2;
 		mb();
-		*((unsigned int *)APECS_IOC_HAXR2) = haxr2 | 1;
+		*(vuip)APECS_IOC_HAXR2 = haxr2 | 1;
 		DBG(("conf_read: TYPE1 access\n"));
 	}
 
@@ -159,8 +160,7 @@
 	apecs_mcheck_taken = 0;
 	mb();
 	/* access configuration space: */
-	value = *((volatile unsigned int *)addr);
-	mb();
+	value = *(vuip)addr;
 	mb();
 	if (apecs_mcheck_taken) {
 		apecs_mcheck_taken = 0;
@@ -169,17 +169,18 @@
 	}
 	apecs_mcheck_expected = 0;
 	mb();
+
+#if 1
 	/*
 	 * david.rusling@reo.mts.dec.com.  This code is needed for the
 	 * EB64+ as it does not generate a machine check (why I don't
 	 * know).  When we build kernels for one particular platform
 	 * then we can make this conditional on the type.
 	 */
-#if 1
 	draina();
 
 	/* now look for any errors */
-	stat0 = *((unsigned int *)APECS_IOC_DCSR);
+	stat0 = *(vuip)APECS_IOC_DCSR;
 	DBG(("conf_read: APECS DCSR after read 0x%x\n", stat0));
 	if (stat0 & 0xffe0U) { /* is any error bit set? */
 		/* if not NDEV, print status */
@@ -188,7 +189,7 @@
 		}
 
 		/* reset error status: */
-		*((volatile unsigned long *)APECS_IOC_DCSR) = stat0;
+		*(vulp)APECS_IOC_DCSR = stat0;
 		mb();
 		wrmces(0x7);			/* reset machine check */
 		value = 0xffffffff;
@@ -197,7 +198,7 @@
 
 	/* if Type1 access, must reset HAE #2 so normal IO space ops work */
 	if (type1) {
-		*((unsigned int *)APECS_IOC_HAXR2) = haxr2 & ~1;
+		*(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;
 		mb();
 	}
 	restore_flags(flags);
@@ -224,37 +225,37 @@
 	cli();
 
 	/* reset status register to avoid losing errors: */
-	stat0 = *((volatile unsigned int *)APECS_IOC_DCSR);
-	*((volatile unsigned int *)APECS_IOC_DCSR) = stat0;
+	stat0 = *(vuip)APECS_IOC_DCSR;
+	*(vuip)APECS_IOC_DCSR = stat0;
 	mb();
 
 	/* if Type1 access, must set HAE #2 */
 	if (type1) {
-		haxr2 = *((unsigned int *)APECS_IOC_HAXR2);
+		haxr2 = *(vuip)APECS_IOC_HAXR2;
 		mb();
-		*((unsigned int *)APECS_IOC_HAXR2) = haxr2 | 1;
+		*(vuip)APECS_IOC_HAXR2 = haxr2 | 1;
 	}
 
 	draina();
 	apecs_mcheck_expected = 1;
 	mb();
 	/* access configuration space: */
-	*((volatile unsigned int *)addr) = value;
-	mb();
+	*(vuip)addr = value;
 	mb();
 	apecs_mcheck_expected = 0;
 	mb();
+
+#if 1
 	/*
 	 * david.rusling@reo.mts.dec.com.  This code is needed for the
 	 * EB64+ as it does not generate a machine check (why I don't
 	 * know).  When we build kernels for one particular platform
 	 * then we can make this conditional on the type.
 	 */
-#if 1
 	draina();
 
 	/* now look for any errors */
-	stat0 = *((unsigned int *)APECS_IOC_DCSR);
+	stat0 = *(vuip)APECS_IOC_DCSR;
 	if (stat0 & 0xffe0U) { /* is any error bit set? */
 		/* if not NDEV, print status */
 		if (!(stat0 & 0x0800)) {
@@ -262,7 +263,7 @@
 		}
 
 		/* reset error status: */
-		*((volatile unsigned long *)APECS_IOC_DCSR) = stat0;
+		*(vulp)APECS_IOC_DCSR = stat0;
 		mb();
 		wrmces(0x7);			/* reset machine check */
 	}
@@ -270,7 +271,7 @@
 
 	/* if Type1 access, must reset HAE #2 so normal IO space ops work */
 	if (type1) {
-		*((unsigned int *)APECS_IOC_HAXR2) = haxr2 & ~1;
+		*(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;
 		mb();
 	}
 	restore_flags(flags);
@@ -433,7 +434,7 @@
 #ifdef CONFIG_ALPHA_CABRIOLET
 	/*
 	 * JAE: HACK!!! for now, hardwire if configured...
-	 * davidm: Older miniloader versions don't set the clockfrequency
+	 * davidm: Older miniloader versions don't set the clock frequency
 	 * right, so hardcode it for now.
 	 */
 	if (hwrpb->sys_type == ST_DEC_EB64P) {
@@ -448,7 +449,9 @@
 	    unsigned long *l, sum;
 
 	    sum = 0;
-	    for (l = (unsigned long *) hwrpb; l < (unsigned long *) &hwrpb->chksum; ++l)
+	    for (l = (unsigned long *) hwrpb;
+		 l < (unsigned long *) &hwrpb->chksum;
+		 ++l)
 	      sum += *l;
 	    hwrpb->chksum = sum;
 	}
@@ -462,10 +465,10 @@
         */
        {
 #if 0
-         unsigned int haxr2 = *((unsigned int *)APECS_IOC_HAXR2); mb();
+         unsigned int haxr2 = *(vuip)APECS_IOC_HAXR2; mb();
          if (haxr2) printk("apecs_init: HAXR2 was 0x%x\n", haxr2);
 #endif
-         *((unsigned int *)APECS_IOC_HAXR2) = 0; mb();
+         *(vuip)APECS_IOC_HAXR2 = 0; mb();
        }
 
 
@@ -474,15 +477,15 @@
 
 int apecs_pci_clr_err(void)
 {
-	apecs_jd = *((unsigned long *)APECS_IOC_DCSR);
+	apecs_jd = *(vulp)APECS_IOC_DCSR;
 	if (apecs_jd & 0xffe0L) {
-		apecs_jd1 = *((unsigned long *)APECS_IOC_SEAR);
-		*((unsigned long *)APECS_IOC_DCSR) = apecs_jd | 0xffe1L;
-		apecs_jd = *((unsigned long *)APECS_IOC_DCSR);
+		apecs_jd1 = *(vulp)APECS_IOC_SEAR;
+		*(vulp)APECS_IOC_DCSR = apecs_jd | 0xffe1L;
+		apecs_jd = *(vulp)APECS_IOC_DCSR;
 		mb();
 	}
-	*((unsigned long *)APECS_IOC_TBIA) = APECS_IOC_TBIA;
-	apecs_jd2 = *((unsigned long *)APECS_IOC_TBIA);
+	*(vulp)APECS_IOC_TBIA = APECS_IOC_TBIA;
+	apecs_jd2 = *(vulp)APECS_IOC_TBIA;
 	mb();
 	return 0;
 }
@@ -547,7 +550,8 @@
 		wrmces(0x1f); /* disable correctable from now on */
 		mb();
 		draina();
-		printk("apecs_machine_check: HW correctable (0x%lx)\n", vector);
+		printk("apecs_machine_check: HW correctable (0x%lx)\n",
+		       vector);
 	}
 	else {
 		printk(KERN_CRIT "APECS machine check:\n");
@@ -572,4 +576,3 @@
 #endif
 	}
 }
-#endif /* CONFIG_ALPHA_APECS */