patch-2.1.103 linux/include/asm-mips/mipsregs.h

• Lines: 34
• Date: Thu May 14 19:01:21 1998
• Orig file: v2.1.102/linux/include/asm-mips/mipsregs.h
• Orig date: Fri May 8 23:14:55 1998

diff -u --recursive --new-file v2.1.102/linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h
@@ -317,20 +317,20 @@
 #define  CAUSEF_BD		(1   << 31)
 
 /*
- * Bits in the coprozessor 0 config register.
+ * Bits in the coprocessor 0 config register.
  */
-#define CONFIG_CM_CACHABLE_NO_WA	0
-#define CONFIG_CM_CACHABLE_WA		1
-#define CONFIG_CM_UNCACHED		2
-#define CONFIG_CM_CACHABLE_NONCOHERENT	3
-#define CONFIG_CM_CACHABLE_CE		4
-#define CONFIG_CM_CACHABLE_COW		5
-#define CONFIG_CM_CACHABLE_CUW		6
-#define CONFIG_CM_CACHABLE_ACCELERATED	7
-#define CONFIG_CM_CMASK			7
-#define CONFIG_DB			(1 <<  4)
-#define CONFIG_IB			(1 <<  5)
-#define CONFIG_SC			(1 << 17)
+#define CONF_REG_CM_CACHABLE_NO_WA	0
+#define CONF_REG_CM_CACHABLE_WA		1
+#define CONF_REG_CM_UNCACHED		2
+#define CONF_REG_CM_CACHABLE_NONCOHERENT	3
+#define CONF_REG_CM_CACHABLE_CE		4
+#define CONF_REG_CM_CACHABLE_COW		5
+#define CONF_REG_CM_CACHABLE_CUW		6
+#define CONF_REG_CM_CACHABLE_ACCELERATED	7
+#define CONF_REG_CM_CMASK			7
+#define CONF_REG_DB			(1 <<  4)
+#define CONF_REG_IB			(1 <<  5)
+#define CONF_REG_SC			(1 << 17)
 
 /*
  * R10000 performance counter definitions.