patch-2.3.47 linux/arch/sparc64/kernel/pci_sabre.c

• Lines: 62
• Date: Fri Feb 18 15:07:20 2000
• Orig file: v2.3.46/linux/arch/sparc64/kernel/pci_sabre.c
• Orig date: Wed Feb 16 17:03:51 2000

diff -u --recursive --new-file v2.3.46/linux/arch/sparc64/kernel/pci_sabre.c linux/arch/sparc64/kernel/pci_sabre.c
@@ -1,4 +1,4 @@
-/* $Id: pci_sabre.c,v 1.12 2000/02/08 05:11:33 jj Exp $
+/* $Id: pci_sabre.c,v 1.14 2000/02/18 13:48:55 davem Exp $
  * pci_sabre.c: Sabre specific PCI controller support.
  *
  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
@@ -1105,7 +1105,8 @@
 }
 
 static void __init sabre_iommu_init(struct pci_controller_info *p,
-				    int tsbsize, unsigned long dvma_offset)
+				    int tsbsize, unsigned long dvma_offset,
+				    u32 dma_mask)
 {
 	unsigned long tsbbase, i, order;
 	u64 control;
@@ -1140,6 +1141,7 @@
 	}
 	p->iommu.page_table = (iopte_t *)tsbbase;
 	p->iommu.page_table_map_base = dvma_offset;
+	p->iommu.dma_addr_mask = dma_mask;
 	memset((char *)tsbbase, 0, PAGE_SIZE << order);
 
 	/* Make sure DMA address 0 is never returned just to allow catching
@@ -1312,7 +1314,7 @@
 	int tsbsize, err;
 	u32 busrange[2];
 	u32 vdma[2];
-	u32 upa_portid;
+	u32 upa_portid, dma_mask;
 	int bus;
 
 	p = kmalloc(sizeof(*p), GFP_ATOMIC);
@@ -1372,12 +1374,19 @@
 		prom_halt();
 	}
 
+	dma_mask = vdma[0];
 	switch(vdma[1]) {
 		case 0x20000000:
+			dma_mask |= 0x1fffffff;
 			tsbsize = 64;
 			break;
 		case 0x40000000:
+			dma_mask |= 0x3fffffff;
+			tsbsize = 128;
+			break;
+
 		case 0x80000000:
+			dma_mask |= 0x7fffffff;
 			tsbsize = 128;
 			break;
 		default:
@@ -1385,7 +1394,7 @@
 			prom_halt();
 	}
 
-	sabre_iommu_init(p, tsbsize, vdma[0]);
+	sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
 
 	printk("SABRE: DVMA at %08x [%08x]\n", vdma[0], vdma[1]);