WD90C24 clocks

Information for Western Digital Chipset Users : WD90C24 clocks
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## 4. WD90C24 clocks

Here are some more details on the adjustable clocks:

The VRAM clock (Mclk) is adjusted by adding ONE of the following option lines to the Device section of the `XF86Config`:

> `

>        Option      "slow_dram"     # Set Mclk to 47.429 MHz
>        Option      "med_dram"      # Set Mclk to 49.219 MHz
>        Option      "fast_dram"     # Set Mclk to 55.035 MHz

> `

The default is to leave Mclk as the BIOS sets it. This is 44.297 on many systems. Some systems may not work properly with any of these options. If you experience ``bit errors'' on your display, reduce the Mclk speed, or don't use any of these options. The Mclk is not reset on server exit.

The data book says that the maximum pixel clock is 1.6 times Mclk so you may want to experiment with higher Mclk rates if you have a fast monitor. It also says a 44.297MHz Mclk and 65MHz pixel clock is the fastest the WD90C24A2 is designed to go. However, some success has been reported with faster clocks. Don't expect all the clocks the chip can provide to work properly.

The second and fourth group of 4 clocks are adjustable. That is, clocks 5, 6, 7, 8 and 13, 14, 15, 16 (counting from 1). These clocks are set by the Clocks line. Be sure to adjust the 17th (last) clock to match your Mclk. Here is a sample set of clocks lines with some clocks defined which are not directly provided by the chip. The NON-programmable clocks (1-4 and 9-12) MUST be set as indicated here.

       Clocks     25.175 28.322 65     36     # These are *not* programmable

       Clocks     29.979 77.408 62.195 59.957 # these are programmable
       Clocks     31.5   35.501 75.166 50.114 # these are *not* programmable
       Clocks     39.822 72.038 44.744 80.092 # these are programmable
       Clocks     44.297                      # Change this if you change
                                              #   Mclk above.

You can program the clocks in increments of .447443 MHz. The server will warn you and adjust to the nearest increment if you specify a clock which does not fit this formula. Clocks 1-4 and 9-12 (the fixed clocks) are not constrained to this multiple, but instead are used to provide standard clocks which are not a multiple by .447443 MHz.

If you probe for clocks (for example to find your Mclk), do it in CRT only mode and then add clocks lines in your `XF86Config` file. Clocks will not probe correctly in LCD mode on most systems.

The BIOS on some systems may not allow switching from CRT to LCD unless the correct clock and/or mode is used. Try the following mode line for 640x480 LCD displays.

       ModeLine "640x480"  25.175   640 664 760 800     480 491 493 525 #CRT/LCD

The following modelines have been tested with the above Clocks lines on some systems, and are provided here as examples. Some testers have experienced minor problems (snow) with the fixed 65 and 75.166 MHz dot clocks. The modelines below have been reported to circumvent these problems. Do not assume your monitor will not be damaged by any of these.

     # VESA 800x600@72Hz Non-Interlaced mode
       ModeLine  "800x600.50"  50  800  856  976 1040 600 637 643 666  +hsync +vsync

     # 1024x768  Interlaced mode
       ModeLine  "1024x768i"   45  1024 1048 1208 1264 768 776 784 817 +hsync +vsync Interlace

     # 1024x768@60Hz Non-interlaced Mode
     # One of the dram options may be necessary
       ModeLine  "1024x768.65" 65  1024 1032 1176 1344 768 771 777 806 -hsync -vsync

     # 1024x768@60Hz Non-Interlaced mode (non-standard dot-clock)
     # Seems to work without dram options
       ModeLine  "1024x768.62" 62  1024 1064 1240 1280 768 774 776 808

     # 1024x768@70Hz Non-Interlaced mode (non-standard dot-clock)
     # May need fast_dram option
       ModeLine  "1024x768.72" 72  1024 1056 1192 1280 768 770 776 806 -hsync -vsync

Information for Western Digital Chipset Users : WD90C24 clocks
Previous: WD90C24 features
Next: Additional WD90C24 information