Basic configuration

Information for Cirrus Chipset Users : Basic configuration
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## 2. Basic configuration

It is recommended that you generate an XF86Config file using the ``XF86Setup`' or ``xf86config`' program, which should produce a working high-resolution 8bpp configuration. You may want to include mode timings in the `Monitor` section that better fit your monitor (e.g 1152x900 modes). The driver options are described in detail in the next section; here the basic options are hinted at.

For all chipsets, a `Clockchip "cirrus"` line in the `Device` section can be useful. This allows the use of any dot clocks, instead of one out of the fixed set of dot clocks supported by the driver. This is required if you want a 12.6 MHz dot clock for low-resolution modes. However, when this option used, clock frequencies be unstable leading to strange effects, so only use it if absolutely required.

For any chip with a BitBLT engine, the new XAA (XFree86 Acceleration Architecture) is used. This code is new and still in a beta stage. If graphics redrawing goes wrong, try the `"noaccel"` option; if it is using memory-mapped I/O, `"no_mmio"` might be sufficient.

In order to be able to run at a depth of 16bpp, 24bpp, or 32bpp, and to improve performance at 8bpp, linear addressing must be enabled. This is generally

In order to be able to run at a depth of 16bpp, 24bpp or 32bpp, and to improve performance at 8bpp, linear addressing must be enabled. Linear addressing is the default mode of operation on any PCI-bus configuration; use `"nolinear"` to disable it. For other bus types, it is generally possible on 543x local bus cards, and if you have less than 16Mb of system memory, on local bus 542x cards and ISA 543x cards. You must specify the `"linear"` option and possibly a `Membase` address. See the following sections for a detailed description.

Memory-mapped I/O is the default mode of operation for any Alpine family chip. For the 5429, the `"mmio"` option may be used to enable it, but it has not been tested.

Finally, if you have 546X chip, it will be on the PCI bus. As such, there is no problem about memory mapped I/O or linear frame buffer address spaces running into system memory. The PCI spaces are mapped way up near the 4GB point. Because the mmio and linear frame buffer don't conflict at all on the system, the `"linear"`, `Membase`, and `"mmio"` options are ignored (memory mapped I/O and linear addressing are always used).

Information for Cirrus Chipset Users : Basic configuration
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Next: XF86Config options