patch-2.1.73 linux/arch/mips/kernel/r4k_misc.S

• Lines: 82
• Date: Wed Dec 10 10:31:09 1997
• Orig file: v2.1.72/linux/arch/mips/kernel/r4k_misc.S
• Orig date: Thu Jun 26 12:33:37 1997

diff -u --recursive --new-file v2.1.72/linux/arch/mips/kernel/r4k_misc.S linux/arch/mips/kernel/r4k_misc.S
@@ -1,10 +1,12 @@
-/* $Id: r4k_misc.S,v 1.2 1997/06/12 14:18:10 ralf Exp $
+/*
  * r4k_misc.S: Misc. exception handling code for r4k.
  *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
  *
  * Multi-cpu abstraction and reworking:
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ *
+ * $Id: r4k_misc.S,v 1.3 1997/09/07 04:51:07 ralf Exp $
  */
 #include <asm/asm.h>
 #include <asm/current.h>
@@ -21,7 +23,7 @@
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 
-#define NOTLB_OPTIMIZE /* If you are paranoid, define this. */
+#undef NOTLB_OPTIMIZE /* If you are paranoid, define this. */
 
 	/* ABUSE of CPP macros 101. */
 
@@ -108,10 +110,32 @@
 	.set	noreorder
 	.set	mips3
 
-	/* Note for many R4k variants tlb probes cannot be executed out
+/*
+ * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
+ * 2. A timing hazard exists for the TLBP instruction.
+ *
+ *      stalling_instruction
+ *      TLBP
+ *
+ * The JTLB is being read for the TLBP throughout the stall generated by the
+ * previous instruction. This is not really correct as the stalling instruction
+ * can modify the address used to access the JTLB.  The failure symptom is that
+ * the TLBP instruction will use an address created for the stalling instruction
+ * and not the address held in C0_ENHI and thus report the wrong results.
+ *
+ * The software work-around is to not allow the instruction preceding the TLBP
+ * to stall - make it an NOP or some other instruction guaranteed not to stall.
+ *
+ * Errata 2 will not be fixed.  This errata is also on the R5000.
+ *
+ * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
+ */
+#define R5K_HAZARD nop
+
+	/*
+	 * Note for many R4k variants tlb probes cannot be executed out
 	 * of the instruction cache else you get bogus results.
 	 */
-
 	.align	5
 	NESTED(r4k_handle_tlbl, PT_SIZE, sp)
 	.set	noat
@@ -120,6 +144,7 @@
 #ifndef NOTLB_OPTIMIZE
 	/* Test present bit in entry. */
 	LOAD_PTE(k0, k1)
+	R5K_HAZARD
 	tlbp
 	PTE_PRESENT(k0, k1, nopage_tlbl)
 	PTE_MAKEVALID(k0, k1)
@@ -141,6 +166,7 @@
 	.set	noat
 #ifndef NOTLB_OPTIMIZE
 	LOAD_PTE(k0, k1)
+	R5K_HAZARD
 	tlbp				# find faulting entry
 	PTE_WRITABLE(k0, k1, nopage_tlbs)
 	PTE_MAKEWRITE(k0, k1)
@@ -162,6 +188,7 @@
 	.set	noat
 #ifndef NOTLB_OPTIMIZE
 	LOAD_PTE(k0, k1)
+	R5K_HAZARD
 	tlbp					# find faulting entry
 	andi	k0, k0, _PAGE_WRITE
 	beqz	k0, nowrite_mod