* Qualcomm Atheros ath10k wireless devices

Required properties:
- compatible: Should be one of the following:
	* "qcom,ath10k"
	* "qcom,ipq4019-wifi"
	* "qcom,wcn3990-wifi"

PCI based devices uses compatible string "qcom,ath10k" and takes calibration
data along with board specific data via "qcom,ath10k-calibration-data".
Rest of the properties are not applicable for PCI based devices.

AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
and also uses most of the properties defined in this doc (except
"qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
to carry pre calibration data.

In general, entry "qcom,ath10k-pre-calibration-data" and
"qcom,ath10k-calibration-data" conflict with each other and only one
can be provided per device.

SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".

Optional properties:
- reg: Address and length of the register set for the device.
- reg-names: Must include the list of following reg names,
	     "membase"
- resets: Must contain an entry for each entry in reset-names.
          See ../reset/reseti.txt for details.
- reset-names: Must include the list of following reset names,
	       "wifi_cpu_init"
	       "wifi_radio_srif"
	       "wifi_radio_warm"
	       "wifi_radio_cold"
	       "wifi_core_warm"
	       "wifi_core_cold"
- clocks: List of clock specifiers, must contain an entry for each required
          entry in clock-names.
- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
               "wifi_wcss_rtc".
- interrupts: List of interrupt lines. Must contain an entry
	      for each entry in the interrupt-names property.
- interrupt-names: Must include the entries for MSI interrupt
		   names ("msi0" to "msi15") and legacy interrupt
		   name ("legacy"),
- qcom,msi_addr: MSI interrupt address.
- qcom,msi_base: Base value to add before writing MSI data into
		MSI address register.
- qcom,ath10k-calibration-variant: string to search for in the board-2.bin
				   variant list with the same bus and device
				   specific ids
- qcom,ath10k-calibration-data : calibration data + board specific data
				 as an array, the length can vary between
				 hw versions.
- qcom,ath10k-pre-calibration-data : pre calibration data as an array,
				     the length can vary between hw versions.
- <supply-name>-supply: handle to the regulator device tree node
			   optional "supply-name" is "vdd-0.8-cx-mx".
- memory-region:
	Usage: optional
	Value type: <phandle>
	Definition: reference to the reserved-memory for the msa region
		    used by the wifi firmware running in Q6.

Example (to supply the calibration data alone):

In this example, the node is defined as child node of the PCI controller.

pci {
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";

		ath10k@0,0 {
			reg = <0 0 0 0 0>;
			device_type = "pci";
			qcom,ath10k-calibration-data = [ 01 02 03 ... ];
		};
	};
};

Example (to supply ipq4019 SoC wifi block details):

wifi0: wifi@a000000 {
	compatible = "qcom,ipq4019-wifi";
	reg = <0xa000000 0x200000>;
	resets = <&gcc WIFI0_CPU_INIT_RESET>,
		 <&gcc WIFI0_RADIO_SRIF_RESET>,
		 <&gcc WIFI0_RADIO_WARM_RESET>,
		 <&gcc WIFI0_RADIO_COLD_RESET>,
		 <&gcc WIFI0_CORE_WARM_RESET>,
		 <&gcc WIFI0_CORE_COLD_RESET>;
	reset-names = "wifi_cpu_init",
		      "wifi_radio_srif",
		      "wifi_radio_warm",
		      "wifi_radio_cold",
		      "wifi_core_warm",
		      "wifi_core_cold";
	clocks = <&gcc GCC_WCSS2G_CLK>,
		 <&gcc GCC_WCSS2G_REF_CLK>,
		 <&gcc GCC_WCSS2G_RTC_CLK>;
	clock-names = "wifi_wcss_cmd",
		      "wifi_wcss_ref",
		      "wifi_wcss_rtc";
	interrupts = <0 0x20 0x1>,
		     <0 0x21 0x1>,
		     <0 0x22 0x1>,
		     <0 0x23 0x1>,
		     <0 0x24 0x1>,
		     <0 0x25 0x1>,
		     <0 0x26 0x1>,
		     <0 0x27 0x1>,
		     <0 0x28 0x1>,
		     <0 0x29 0x1>,
		     <0 0x2a 0x1>,
		     <0 0x2b 0x1>,
		     <0 0x2c 0x1>,
		     <0 0x2d 0x1>,
		     <0 0x2e 0x1>,
		     <0 0x2f 0x1>,
		     <0 0xa8 0x0>;
	interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
			  "msi4",  "msi5",  "msi6",  "msi7",
			  "msi8",  "msi9",  "msi10", "msi11",
			  "msi12", "msi13", "msi14", "msi15",
			  "legacy";
	qcom,msi_addr = <0x0b006040>;
	qcom,msi_base = <0x40>;
	qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
};

Example (to supply wcn3990 SoC wifi block details):

wifi@18000000 {
		compatible = "qcom,wcn3990-wifi";
		reg = <0x18800000 0x800000>;
		reg-names = "membase";
		clocks = <&clock_gcc clk_aggre2_noc_clk>;
		clock-names = "smmu_aggre2_noc_clk"
		interrupts =
			   <0 130 0 /* CE0 */ >,
			   <0 131 0 /* CE1 */ >,
			   <0 132 0 /* CE2 */ >,
			   <0 133 0 /* CE3 */ >,
			   <0 134 0 /* CE4 */ >,
			   <0 135 0 /* CE5 */ >,
			   <0 136 0 /* CE6 */ >,
			   <0 137 0 /* CE7 */ >,
			   <0 138 0 /* CE8 */ >,
			   <0 139 0 /* CE9 */ >,
			   <0 140 0 /* CE10 */ >,
			   <0 141 0 /* CE11 */ >;
		vdd-0.8-cx-mx-supply = <&pm8998_l5>;
		memory-region = <&wifi_msa_mem>;
};
